New Design of Capillaries for Multi-Tier Wire Bonding

The demand for increased computing power and more complex integrated circuit devices with increased functions per chip results in high lead-count integrated circuit packages. With the shrinkage in integrated circuit sizes towards smaller packages, and the decrease in pad pitch, the trend is moving from the current ultra-fine-pitch volume production of 50 μm to even lower pad pitches. However, the various concerns for 50-μm pitch bonding, such as low production yield, reliability issues, etc, have forced many customers to re-visit the feasibility of utilising the robust fine pitch bonding to handle the high lead-count packages. This paper reports the new development of bonding tools to handle the multi-tier wire bonding requirement with a maximum loop height of 475 μm. With the increase in the loop height of the wires, the bottleneck height of the capillary needs to be increased accordingly to prevent touching the adjacent wire during bonding. The increase in bottleneck height can influence the efficient transfer of the ultrasonic energy from the bonding tool to the bond interface and affect bond quality. In addition, the longer bottleneck height of the capillary also increases the risk of tip breakage during bonding. In this study, the external profile of the capillary is simulated with respect to the looping profile during bonding using a customised software package. In addition, finite element simulation is also utilised to analyse the difference in stress level with different bonding tool designs. The results of the simulations are then used to correlate with the actual bonding responses. Key-Words: Wire bonding, integrated circuit, capillary, design, fine pitch, stress.